教育背景
1998.09-2002.06 濟南大學計算機系,學士
2005.09-2008.03 東北電力大學,計算機應用,碩士
2008.09-2012.04 大連理工大學,電路與系統,博士
工作簡歷
2012.05-2015.05 中國科學院微電子研究所,博士后,合作導師:萬里兮
2015.05-2018.03中國科學院微電子研究所,助理研究員一級
2018.04 至今 中國科學院微電子研究所, 副研究員
1. 國家重大專項: 28nm CPU封裝協同設計與仿真,項目負責人
2. 國家重大專項:-板級扇出封裝集成設計和產品技術研究,首席科學家
3. 中國科學院科創計劃:系統級扇出封裝的熱管理研究,項目負責人
4. 北京高校實培計劃:基于先進封裝的多場耦合分析,項目負責人
[1] M. Su, L. Cao, T. Lin, F. Chen, J. Li, C. Chen, et al., "Warpage simulation and experimental verification for 320?mm?×?320?mm panel level fan-out packaging based on die-first process," Microelectronics Reliability, vol. 83, pp. 29-38, 2018/04/01/ 2018.
[2] M. Su, D. Yu, Y. Liu, L. Wan, C. Song, F. Dai, et al., "Properties and electric characterizations of tetraethyl orthosilicate-based plasma enhanced chemical vapor deposition oxide film deposited at 400°C for through silicon via application," Thin Solid Films, vol. 550, pp. 259-263, 2014/01/01/ 2014.
[3] M. Su, X. Zhang, L. Wan, D. Yu, X. Jing, Z. Fang, et al., "Temperature-dependant thermal stress analysis of through-silicon-vias during manufacturing process," in 2013 14th International Conference on Electronic Packaging Technology, 2013, pp. 551-554.
[4] M. Su, C. Chen, M. Zhou, J. Li, and L. Cao, "Warpage Prediction and Lifetime Analysis for Large Size Through-silicon-via (TSV) Interposer Package," in 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 2018, pp. 387-390.
1. 一種TSV孔內介質層的電學性能無損檢測方法,201410841720.0,授權
2. 基于柔性基板的三維封裝散熱結構及其制備方法,201510312334.7,授權
3. 一種基于載體的扇出2.5D/3D封裝結構的制造方法,201510970167.5,授權
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